drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link

For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.

v2: Address review comments by Jani
    - Added wait time for PLL to be locked.

v3: separate patch created for cck read for checking PLL to be locked

Signed-off-by: Gaurav K Singh <57d7670cd3ba6c6bdc1f4d87dfd208f6d77f3ca8@intel.com>
Signed-off-by: Shobhit Kumar <255d4827ed4cdfb7622c11dc83842a9187d70ef7@intel.com>
Reviewed-by: Jani Nikula <ba783f3beccaedfda693f41a15407d612a629408@intel.com>
Signed-off-by: Daniel Vetter <c1b6782c4af8f0673da8923a0702a1832e5940f4@ffwll.ch>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs