clk: socfpga: Support multiple parents for the pll clocks
clk: socfpga: Support multiple parents for the pll clocks

The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk.
Update the clock driver to be able to get the correct parent.

Signed-off-by: Dinh Nguyen <a48724738fc762a7f206428dfcaf7ede2fd84d0f@altera.com>
Cc: Steffen Trumtrar <acd73cdea7391c1e626e2d4b16b2f41438ca5396@pengutronix.de>
Signed-off-by: Mike Turquette <6dab61939fc5e23761050a66932f032dceda5ebf@linaro.org>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs