it83xx: clock: fix sequence to set PLL control register
it83xx: clock: fix sequence to set PLL control register

We change event timer's clock to 32.768kHz before entering low power
mode. And will restore the clock to 8MHz (by checking PLL control
register's setting in ISR) when chip wake up from the low power mode.
So we need to ensure the setting is taken into PLL control register
before wfi instruction. The original implementation can't ensure event
timer’s clock is restored to 8MHz when chip wake up. So we fix it.

This also fix wfi (wait for interrupt) instruction fail issue on RISV-V
core chips when a timer count down to zero (MTIP@mip is set to 1 until
HW reload timer counter).
Once CPU executed wfi instruction, CPU should stay there until interrupt
is fired or MEIP@mip is non-zero. But currently, HW checks entire mip
value (should check MEIP@mip only) to decide whether or not to ignore
wfi instruction.
The issue will cause EC premature wake from idle task even there is no
interrupt fired.

BRANCH=asurada, icarus
BUG=none
TEST=-On asurada, increase CPU clock to 96mhz.
      Plug out/in type-c adapter to wake chip up from low power mode,
      no pre-watchdog warning fired. (x100)
     -buildall

Signed-off-by: Dino Li <338d523ecf3700bd86eb9c34d220f91911d2a18c@ite.com.tw>
Change-Id: I72bb2566c5b22bc132ab304a38a5a1b5b968e463
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3168672
Reviewed-by: Eric Yilun Lin <2f2733c7206ea2b76bd2db1905cc5e8a75841c48@google.com>
Commit-Queue: Eric Yilun Lin <2f2733c7206ea2b76bd2db1905cc5e8a75841c48@google.com>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec