i965/fs: Don't follow pow with an instruction with two dest regs.
i965/fs: Don't follow pow with an instruction with two dest regs.

Beginning with commit 7b208a73, Unigine Valley began hanging the GPU on
Gen >= 8 platforms.

Evidently that commit allowed the scheduler to make different choices
that somehow finally ran afoul of a hardware bug in which POW and FDIV
instructions may not be followed by an instruction with two destination
registers (including compressed instructions). I presume the conditions
are more complex than that, but the internal hardware bug report (BDWGFX
bug_de 1696294) does not contain much more information.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94924
Reviewed-by: Topi Pohjolainen <749697f19798b7f640b17221fd283b903825f071@intel.com> [v1]
Tested-by:  Mark Janes <dc19c7a5044e1b627d35321fa5e1121fad8638f9@intel.com> [v1]
Reviewed-by: Francisco Jerez <5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net>

metora/MesaGLSLCompiler,metora/MesaGLSLCompiler,metora/MesaGLSLCompiler