[ci] Perform a bitstream load at the start of tests to clear FPGA state.
[ci] Perform a bitstream load at the start of tests to clear FPGA state.

Signed-off-by: Drew Macrae <32d48ac45113625c0a04afe7343eae478a303684@google.com>

lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan