[top/cw305] Generate top for new external ports
[top/cw305] Generate top for new external ports

Re-generated TOP and revise the ASIC, FPGA, VERILATOR chip_top design to
have revised ports.

Carried over from: lowrisc/opentitan#3098

Signed-off-by: Miguel Osorio <c7c97b215f812c2e8a32efd57ad5e976a6eb9e45@google.com>

lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan