ARM: Make sure ldm exception return writes back its base in the right mode.
ARM: Make sure ldm exception return writes back its base in the right mode.

This change moves the writeback of load multiple instructions to the beginning
of the macroop. That way, the MicroLdrRetUop that changes the mode will
necessarily happen later, ensuring the writeback happens in the original mode.
The actual value in the base register if it also shows up in the register list
is undefined, so it's fine if it gets clobbered by one of the loads. For
stores where the base register is the lowest numbered in the register list,
the original value should be written back. That means stores can't write back
at the beginning, but the mode changing problem doesn't affect them so they
can continue to write back at the end.

briancoutinho0905/2dsampling,rjschof/gem5,rallylee/gem5,KuroeKurose/gem5,markoshorro/gem5,rjschof/gem5,kaiyuanl/gem5,kaiyuanl/gem5,gedare/gem5,briancoutinho0905/2dsampling,joerocklin/gem5,aclifton/cpeg853-gem5,TUD-OS/gem5-dtu,SanchayanMaity/gem5,qizenguf/MLC-STT,cancro7/gem5,kaiyuanl/gem5,samueldotj/TeeRISC-Simulator,sobercoder/gem5,joerocklin/gem5,kaiyuanl/gem5,yb-kim/gemV,yb-kim/gemV,HwisooSo/gemV-update,SanchayanMaity/gem5,aclifton/cpeg853-gem5,markoshorro/gem5,cancro7/gem5,zlfben/gem5,SanchayanMaity/gem5,gedare/gem5,HwisooSo/gemV-update,austinharris/gem5-riscv,cancro7/gem5,gem5/gem5,aclifton/cpeg853-gem5,austinharris/gem5-riscv,gedare/gem5,SanchayanMaity/gem5,gem5/gem5,qizenguf/MLC-STT,yb-kim/gemV,markoshorro/gem5,joerocklin/gem5,powerjg/gem5-ci-test,samueldotj/TeeRISC-Simulator,briancoutinho0905/2dsampling,powerjg/gem5-ci-test,rallylee/gem5,aclifton/cpeg853-gem5,gem5/gem5,zlfben/gem5,markoshorro/gem5,cancro7/gem5,briancoutinho0905/2dsampling,briancoutinho0905/2dsampling,TUD-OS/gem5-dtu,gedare/gem5,kaiyuanl/gem5,aclifton/cpeg853-gem5,HwisooSo/gemV-update,briancoutinho0905/2dsampling,gedare/gem5,gedare/gem5,austinharris/gem5-riscv,qizenguf/MLC-STT,Weil0ng/gem5,powerjg/gem5-ci-test,aclifton/cpeg853-gem5,kaiyuanl/gem5,yb-kim/gemV,joerocklin/gem5,rallylee/gem5,yb-kim/gemV,sobercoder/gem5,sobercoder/gem5,samueldotj/TeeRISC-Simulator,gem5/gem5,HwisooSo/gemV-update,SanchayanMaity/gem5,briancoutinho0905/2dsampling,rjschof/gem5,powerjg/gem5-ci-test,Weil0ng/gem5,zlfben/gem5,markoshorro/gem5,austinharris/gem5-riscv,cancro7/gem5,gem5/gem5,gem5/gem5,sobercoder/gem5,rallylee/gem5,rjschof/gem5,Weil0ng/gem5,sobercoder/gem5,samueldotj/TeeRISC-Simulator,markoshorro/gem5,yb-kim/gemV,qizenguf/MLC-STT,samueldotj/TeeRISC-Simulator,markoshorro/gem5,TUD-OS/gem5-dtu,rallylee/gem5,joerocklin/gem5,TUD-OS/gem5-dtu,samueldotj/TeeRISC-Simulator,Weil0ng/gem5,cancro7/gem5,sobercoder/gem5,HwisooSo/gemV-update,TUD-OS/gem5-dtu,aclifton/cpeg853-gem5,rjschof/gem5,KuroeKurose/gem5,sobercoder/gem5,KuroeKurose/gem5,gem5/gem5,yb-kim/gemV,austinharris/gem5-riscv,KuroeKurose/gem5,qizenguf/MLC-STT,Weil0ng/gem5,KuroeKurose/gem5,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,qizenguf/MLC-STT,samueldotj/TeeRISC-Simulator,joerocklin/gem5,zlfben/gem5,Weil0ng/gem5,rjschof/gem5,Weil0ng/gem5,powerjg/gem5-ci-test,rallylee/gem5,zlfben/gem5,powerjg/gem5-ci-test,kaiyuanl/gem5,HwisooSo/gemV-update,rjschof/gem5,gedare/gem5,TUD-OS/gem5-dtu,KuroeKurose/gem5,zlfben/gem5,SanchayanMaity/gem5,austinharris/gem5-riscv,yb-kim/gemV,joerocklin/gem5,cancro7/gem5,KuroeKurose/gem5,HwisooSo/gemV-update,SanchayanMaity/gem5,joerocklin/gem5,austinharris/gem5-riscv,zlfben/gem5,qizenguf/MLC-STT,rallylee/gem5