adlrvp: Cache BB retimer's power state
adlrvp: Cache BB retimer's power state

Ports with cascaded retimers share common load switch and reset pin
hence no need to set the power state of retimer again if the 1st
retimer's power status has already changed. Otherwise, it will add
additional delay to enable the 2nd retimer. Thus, added code to
cache the power state of the retimer per port instead of individual
retimer.

BUG=none
BRANCH=none
TEST=Tested on ADL-P-DDR5 board that has cascaded retimer topology,
     no delay added when enabling SOC side retimer.

Change-Id: I4b67b6aca96bf20776424b3e56f382b021d4084d
Signed-off-by: Vijay Hiremath <006c712879a3af08bfdb5c2b8491a8b2d5fd73cd@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2954730
Reviewed-by: caveh jalali <08e24a66aefda7a55ca7d73f8903e0fb16eec763@chromium.org>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec