[rdc] USBDEV waiver for SW RST REQ scn
[rdc] USBDEV waiver for SW RST REQ scn

In SW reset request scenario, the reset signal is asserted and
de-asserted synchronized to the clock. In this case, any metastability
issue won't occur if the source signal and the end signal are in the
same clock domain.

This commit waives the errors.

Signed-off-by: Eli Kim <3ca62a2ad87376be2697209a1770e1afdbbba220@opentitan.org>

lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan