soc: riscv: riscv-privilege: andes_v5: added SMU register macros
soc: riscv: riscv-privilege: andes_v5: added SMU register macros

Added Wake-Up Reset Status Register macros for hwinfo driver usage.

Signed-off-by: Jimmy Zheng <2028f46ad60f8b8fd2dcf38de94ec39988567df5@andestech.com>

finikorg/zephyr,zephyrproject-rtos/zephyr,zephyrproject-rtos/zephyr,finikorg/zephyr,finikorg/zephyr,galak/zephyr,zephyrproject-rtos/zephyr,galak/zephyr,zephyrproject-rtos/zephyr,galak/zephyr,galak/zephyr,galak/zephyr,zephyrproject-rtos/zephyr,finikorg/zephyr,finikorg/zephyr