dmaengine: fix interrupt clearing for mv_xor
dmaengine: fix interrupt clearing for mv_xor

When using simultaneously the two DMA channels on a same engine, some
transfers are never completed. For example, an endless lock can occur
while writing heavily on a RAID5 array (with async-tx offload support
enabled).

Note that this issue can also be reproduced by using the DMA test
client.

On a same engine, the interrupt cause register is shared between two
DMA channels. This patch make sure that the cause bit is only cleared
for the requested channel.

Signed-off-by: Simon Guinot <53bf830fa8e82969eaab534c14d8e8b9a7a96894@lacie.com>
Tested-by: Luc Saillard <5dc35fa9b5181cf374d77ada02f42716f255ae42@saillard.org>
Acked-by: Saeed Bishara <6964a9a5a8675ef826f55537fdd24b3f21b865b9@marvell.com>
Signed-off-by: Nicolas Pitre <d659c10e27d52b00987b65e85d99bce5480adcae@fluxnic.net>

TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs,KristFoundation/Programs,TeamVee-Kanas/android_kernel_samsung_kanas,TeamVee-Kanas/android_kernel_samsung_kanas,TeamVee-Kanas/android_kernel_samsung_kanas,TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs