ASoC: wm8940: Fix setting PLL Output clock division ratio
ASoC: wm8940: Fix setting PLL Output clock division ratio

According to the datasheet:
The PLL Output clock division ratio is controlled by BIT[5:4] of
WM8940_GPIO register(08h).
Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.

Signed-off-by: Axel Lin <b6ffd6973e972cb999e8e535ab74da7fee0c035f@gmail.com>
Acked-by: Liam Girdwood <a57ef363056e61beffa2efa59c68550d40db03b0@ti.com>
Signed-off-by: Mark Brown <b51b9a92386687a9ac927cebfa0f978adeb8cea5@opensource.wolfsonmicro.com>

KristFoundation/Programs,KristFoundation/Programs,TeamVee-Kanas/android_kernel_samsung_kanas,TeamVee-Kanas/android_kernel_samsung_kanas,TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs,KristFoundation/Programs,TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs,TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs