read_aiger to ignore output = input of same wire; also create new output for different wire
read_aiger to ignore output = input of same wire; also create new output for different wire

antmicro/yosys,SymbiFlow/yosys,cliffordwolf/yosys,SymbiFlow/yosys,SymbiFlow/yosys,cliffordwolf/yosys,antmicro/yosys,YosysHQ/yosys,YosysHQ/yosys,antmicro/yosys,YosysHQ/yosys,cliffordwolf/yosys,cliffordwolf/yosys,SymbiFlow/yosys,cliffordwolf/yosys,YosysHQ/yosys,SymbiFlow/yosys,SymbiFlow/yosys,antmicro/yosys,YosysHQ/yosys,YosysHQ/yosys,antmicro/yosys,cliffordwolf/yosys,antmicro/yosys,antmicro/yosys,cliffordwolf/yosys,SymbiFlow/yosys,YosysHQ/yosys,antmicro/yosys,SymbiFlow/yosys,cliffordwolf/yosys,YosysHQ/yosys,cliffordwolf/yosys