[otbn,dv] Don't fetch next instruction in sim when stalled
[otbn,dv] Don't fetch next instruction in sim when stalled

OTBN used to fetch the next instruction from memory on every cycle. If
memory changed under its feet in the middle of a multi-cycle
instruction, we'd see the integrity error on the next cycle. With the
prefetch stage, this works differently. Now we ignore responses from
IMEM unless we're unblocked (and can put something new into the
prefetch buffer).

This 1-line commit updates the ISS model to work the same way, fixing
failures in the otbn_imem_err sequence which was failing whenever we
happened to inject the error in the middle of a multi-cycle
instruction. Since reads from RND are sloooooow, this happened quite
frequently.

Signed-off-by: Rupert Swarbrick <290093e2ad2515ed2f14d749293c8cf8e02ca274@lowrisc.org>

lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan