i965/gen4-5: Enable 16-wide dispatch on shaders with control flow.
i965/gen4-5: Enable 16-wide dispatch on shaders with control flow.

This was probably disabled due to a combination of several bugs in the
generator code (fixed earlier in this series) and a misunderstanding
of the hardware spec.  The documentation for most control flow
instructions mentions among other restrictions:

 "Instruction compression is not allowed."

This however doesn't have any implications on 16 wide not being
supported, because none of the control flow instructions have
multi-register operands (control flow instructions are not compressed
on more recent hardware either, except maybe SNB's IF with inline
compare).  In fact Gen4-5 had 16-wide control flow masks and stacks,
and the spec mentions in several places that control flow instructions
push and pop 16 channels worth of data -- Otherwise there doesn't seem
to be any indication that it shouldn't work.

Causes no piglit regressions, and gives the following shader-db
results on ILK:

 total instructions in shared programs: 4711384 -> 4711384 (0.00%)
 instructions in affected programs:     0 -> 0
 helped:                                0
 HURT:                                  0
 GAINED:                                1215
 LOST:                                  0

Reviewed-by: Matt Turner <789b315743a28dd066a4ba1459c35951c291d8a6@gmail.com>
Reviewed-by: Kenneth Graunke <bd2562f754ec92342f93f61c25d731e290a2ffa8@whitecape.org>

metora/MesaGLSLCompiler,metora/MesaGLSLCompiler,metora/MesaGLSLCompiler