power/icelake: JSL: add wait loop for receiving ALL_SYS_PWRGD
power/icelake: JSL: add wait loop for receiving ALL_SYS_PWRGD

In some boot cycles, identified a case where PG_DRAM_OD
not getting SET when EC already transitioned to S0.
PG_DRAM_OD taking around 5+ms to get SET, after SLP_S3_L SET.
In such cases, intel_x86_get_pg_ec_all_sys_pwrgd() returns 0
and PCH_SYS_PWROK remaining as 0.

BUG=b:147257114
BRANCH=None
TEST=make -j BOARD=waddledoo; flash waddledoo, verify that
DUT can boot to S0.

Change-Id: I09207c723d3d006e8a555c3c2d44aa6ed5cc027d
Signed-off-by: Sooraj Govindan <d85e88211a48c826cfa21b207bd3d4813059f1ed@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2054363
Tested-by: Sooraj Govindan <d85e88211a48c826cfa21b207bd3d4813059f1ed@intel.corp-partner.google.com>
Reviewed-by: Aseda Aboagye <12c9b286316a940fd31c24070da5ab64cdd4d0e7@chromium.org>
Commit-Queue: Aseda Aboagye <12c9b286316a940fd31c24070da5ab64cdd4d0e7@chromium.org>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec