arc: hsdk: Set SRAM_BASE_ADDRESS in defconfig
arc: hsdk: Set SRAM_BASE_ADDRESS in defconfig

On power-on boot-ROM is mapped to address 0 in HSDK board.
Normally later when U-Boot gets started by boot-ROM we change mappings
so that real DDR is mapped to entire address space including 0:
https://elixir.bootlin.com/u-boot/latest/source/board/synopsys/hsdk/hsdk.c#L474

But if U-Boot is not started (which is controlled by the BIM dip-switch
on the board) boot-ROM remains mapped to 0, and essentially any attempt
to write to that location fails, thus we cannot upload contents of our
target Elf there even with JTAG.

The next logical option is to use beginning of the non-translated
memory region 0x8000_0000 which we typically use for loading
U-Boot & Linux kernel on ARC boards. But in case of HSDK
we have DCCM (Data Closely-Coupled MEmory - fast on-chip SRAM)
mapped there and since we cannot execute code from DCCM
we need to skip that region as well which gives us the next option
being 0x9000_0000 . That's because DCCM owns entire 256 MiB "aperture"
even though it may have much smaller size up-to 8 MiB.

We are mapping only 5 apertures because the last two
(0xe000_0000-0xffff_ffff) are used for peripherals and AXI.

Signed-off-by: Evgeniy Didin <5435af8d1d1b65d63b9ec68a39e143f1f5881d59@synopsys.com>
Signed-off-by: Alexey Brodkin <1fa739873496c8c0c1b521f2061ee5fa4a0306e8@synopsys.com>

Vudentz/zephyr,Vudentz/zephyr,finikorg/zephyr,zephyrproject-rtos/zephyr,Vudentz/zephyr,finikorg/zephyr,galak/zephyr,galak/zephyr,finikorg/zephyr,galak/zephyr,galak/zephyr,zephyrproject-rtos/zephyr,nashif/zephyr,zephyrproject-rtos/zephyr,zephyrproject-rtos/zephyr,Vudentz/zephyr,Vudentz/zephyr,nashif/zephyr,galak/zephyr,nashif/zephyr,finikorg/zephyr,nashif/zephyr,nashif/zephyr,zephyrproject-rtos/zephyr,Vudentz/zephyr,finikorg/zephyr