adlrvpp_ite: enable internal pull-up for GPGO
adlrvpp_ite: enable internal pull-up for GPGO

It is observed that PD port 3 has TCPC interrupt storm, the TCPC
interrupt pin GPJ3 stays active low even no interrupt coming. The root
cause is GPJ3 is configured as voltage comparator by GPG0 after EC power
on. Remove GPGO external pull-up resistor to fix this issue.

GPGO is PD port 1 TCPC interrupt pin, enable internal pull-up since
external pull-up resistor is removed.

BUG=b:200265672
BRANCH=none
TEST=on ADL-P DDR5 RVP, apply CL:3111455 and CL:3114705 to enable low
power mode. Don't see interrupt storm on PD port 3.
Connect Gatkex to PD port 1, enter USB4 mode successfully.
Connect Gatkex to PD port 3, enter USB4 mode successfully.

Signed-off-by: li feng <0fd15d95d647a38d004d7ac9a3d0587bb1c98551@intel.com>
Change-Id: If66011ca86a268556ce69bd06f938c92407217aa
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3193511
Reviewed-by: Vijay Hiremath <006c712879a3af08bfdb5c2b8491a8b2d5fd73cd@intel.com>
Reviewed-by: Dino Li <338d523ecf3700bd86eb9c34d220f91911d2a18c@ite.com.tw>
Reviewed-by: caveh jalali <08e24a66aefda7a55ca7d73f8903e0fb16eec763@chromium.org>
Reviewed-by: Tanu Malhotra <88bcd522e76d112209f1cebbc3fc47e8f6ff3003@intel.com>
Commit-Queue: caveh jalali <08e24a66aefda7a55ca7d73f8903e0fb16eec763@chromium.org>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec