Fix regression of always3.1.8A with VHDL target
Fix regression of always3.1.8A with VHDL target

The patch for pr2516774 exposed a bug which caused
always3.1.8A to fail. This patch corrects that.

The test to decide when to use a sensitivity list
rather than an explicit wait statement wasn't tight enough.

themperek/iverilog,CastMi/iverilog,CastMi/iverilog,CastMi/iverilog,themperek/iverilog,themperek/iverilog