for now, make the entire PS7 module be 'clocked_by axi_clock'. (this is possible only because it is faked that this comes from outside, rather than just being generated by PS7 as fclk_clk0.
for now, make the entire PS7 module be 'clocked_by axi_clock'.
(this is possible only because it is faked that this comes from outside,
rather than just being generated by PS7 as fclk_clk0.

In any case, verilog was generated.

8l/connectal,chenm001/connectal,cambridgehackers/connectal,csail-csg/connectal,8l/connectal,chenm001/connectal,chenm001/connectal,hanw/connectal,csail-csg/connectal,8l/connectal,chenm001/connectal,csail-csg/connectal,cambridgehackers/connectal,csail-csg/connectal,hanw/connectal,chenm001/connectal,hanw/connectal,csail-csg/connectal,cambridgehackers/connectal,hanw/connectal,hanw/connectal,8l/connectal,cambridgehackers/connectal,cambridgehackers/connectal,8l/connectal