chip/mt8192_scp: don't unset the THRI flag unless we are in the UART ISR
chip/mt8192_scp: don't unset the THRI flag unless we are in the UART ISR

Interrupt mechanism of MT8192 SCP has 3 tiers: INTC, global VIC,
local VIC (in RV33).

             +------+            +-------------+     +----------------+
             |      |            |             |     |                |
UART TX -----|      |--GROUP 0 --|             |     |                |
UART RX -----| INTC |--GROUP 1 --| Global VIC  |     |   Local VIC    |
Timer 0 -----|      |--GROUP 2 --|             |     |                |
Timer n -----|      |    .       | (MIEMS,     |-----| (INTC_IRQ_OUT, |
          .  |      |    .       |  MICAUSE,   |     |  INTC_IRQ_...) |
          .  |      |    .       |  MIXXXX...) |     |                |
GIPC 0  -----|      |--GROUP 14--|             |     |                |
          .  +------+            +-------------+     +----------------+

GVIC latches from INTC at a time and notifies LVIC if any group is
asserted.

For example, suppose UART TX corresponds to group 12 and GIPC 0
corresponds to group 7:
(1) GIPC 0 and UART TX are asserted.
(2) GVIC notifies LVIC about the interrupt.
(3) RV33 finds group 7 and group 12 (from INTC_IRQ_OUT) are asserted.

Note that it is a fatal error if RV33 cannot find the corresponding
groups in (3).

GVIC caches the group 7 and group 12 until RV33 writes to bit 7 and bit
12 of MIEMS.  Even though the interrupt source is de-asserted, the GVIC
cache won't get updated.

The most suggested way to handle interrupt in RV33: batch handle them.
However, EC OS doesn't handle multiple interrupts at a time.  EC OS
handles 1 interrupt, acknowledges by writing 1 bit in MIEMS, and sees
if further interrupts from GVIC.

UART TX interrupt can be easily cleared by calling cflush() in anywhere.
To avoid the interrupt source of UART TX being cleared in other ISR,
don't unset the THRI flag unless we are in the UART ISR.

BRANCH=none
BUG=b:157541273
TEST=call cflush() in any ISR

Signed-off-by: Tzung-Bi Shih <5e6f7578cd434ae5b4c9ffe5250f7a87a25045d7@chromium.org>
Change-Id: I2fab7308edce386ea65d0d45e39805d8cc7f4857
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2331984
Reviewed-by: Nicolas Boichat <f3daba1cdc403799935674d3cd4b0e5bd1804232@chromium.org>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec