A few SDRAM controller fixes: - Cleanup: maintain burst counts and address in beats (multiples of data bus width) instead of bytes.  It's easier to translate in one spot than all over the place. - Fix a typo in the store FIFO's enqueue port: it was looking at axi_wvalid instead of axi_wready.  This caused it to queue up a bunch of zeros, which would get written o ut. - Do not start an SDRAM write burst until the store FIFO is full (since the address is latched several cycles before data even begins arriving).
A few SDRAM controller fixes:
- Cleanup: maintain burst counts and address in beats (multiples of data bus width) instead of bytes.  It's easier to translate in one spot than all over the place.
- Fix a typo in the store FIFO's enqueue port: it was looking at axi_wvalid instead of axi_wready.  This caused it to queue up a bunch of zeros, which would get written o
ut.
- Do not start an SDRAM write burst until the store FIFO is full (since the address is latched several cycles before data even begins arriving).

hoangt/NyuziProcessor,hoangt/NyuziProcessor,hoangt/NyuziProcessor,FulcronZ/NyuziProcessor,jbush001/NyuziProcessor,FulcronZ/NyuziProcessor,jbush001/NyuziProcessor,hoangt/NyuziProcessor,jbush001/NyuziProcessor,jbush001/NyuziProcessor,FulcronZ/NyuziProcessor,jbush001/NyuziProcessor,FulcronZ/NyuziProcessor,jbush001/NyuziProcessor