npcx: gpio: Only call ISR for enabled interrupts
npcx: gpio: Only call ISR for enabled interrupts

The GPIOs on npcx are handled in banks of 8, and when processing
an interrupt for a particular bank the ISR is executed for each
GPIO in the bank that has a pending bit set.

If an interrupt in a bank is not enabled (but has fired before so
the pending bit is set) but another one in the same bank is enabled
and asserts, then the ISR both of the GPIOs will be executed because
they both have pending bits set.

This results in the ISR for a disabled interrupt getting executed
when it should not and leads to unexpected behavior.

Masking the GPIOs that are not enabled means only the ISR for the
explicitly enabled GPIOs in that bank will be executed.

Example: With the Eve board we have PCH_SLP_SUS_L on GPIO(6,2) which
is enabled at init time and is in the same WKINTG_1 bank as
TRACKPAD_INT_L on GPIO(7,1) which is not enabled, but I am working
on a patch to enable it.  When going into suspend PCH_SLP_SUS_L asserts,
and that is causing the ISR for both PCH_SLP_SUS_L and TRACKPAD_INT_L
to be executed.  If I try to use TRACKPAD_INT_L as a wake source from
DeepS3 this means the system immediately wakes after going to sleep.

BUG=chrome-os-partner:62224
BRANCH=none
TEST=With an additional patch to enable trackpad wake from S3 on Eve,
observe that the system can enter S3 and stay there instead of immediately
waking up due to the TRACKPAD_INT_L ISR firing when it is not enabled.

Change-Id: Idc66e22c93756faf6c4319980cfb8dfe63e0dfaa
Signed-off-by: Duncan Laurie <70662b43bc1a20b57ded72a2b08be88dd0da4841@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446524
Reviewed-by: Mulin Chao <6bbc5af053a1dfdc363be6857f30de4ac3bcbd16@nuvoton.com>
Reviewed-by: Shawn N <5259333ce42e3ace6a73988cec7115ed9d3a661a@chromium.org>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec