Fix interrupt distribution to multiple CPUs on systems with cascaded PICs. Because slave PICs send all interrupts to their CPU 0 output line (which is routed to a pin on the master PIC), changes to per-CPU register banks like EOI on the slave PIC must be accessed for CPU 0, instead of the CPU actually processing the interrupt.
Fix interrupt distribution to multiple CPUs on systems with cascaded PICs.
Because slave PICs send all interrupts to their CPU 0 output line (which
is routed to a pin on the master PIC), changes to per-CPU register banks
like EOI on the slave PIC must be accessed for CPU 0, instead of the
CPU actually processing the interrupt.

Submitted by:	Andreas Tobler

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