conversion to VHDL: moved validation of port names before assign port_num names in case of 'std_logic_ports=True'
conversion to VHDL: moved validation of port names before assign port_num names in case of 'std_logic_ports=True'

myhdl/myhdl,hgomersall/myhdl,hgomersall/myhdl,jandecaluwe/myhdl,myhdl/myhdl,jck/myhdl,myhdl/myhdl,josyb/myhdl,hgomersall/myhdl,jck/myhdl,josyb/myhdl,jck/myhdl,josyb/myhdl,jandecaluwe/myhdl,jandecaluwe/myhdl