Checking this in to document something that I'm going to remove. This is the first checking with all the defining words for the insns. I "cleverly" tried to share code between registers and reg-pairs, for the inc/dec (really inr/dcr/inx/dcx) insns, and for movi (mvi, lxi). Things as defined will work fine for inc/dec, but I neglected to compile the 8- or 16-bit immed value, and realized that it's too much trouble and complication.
Checking this in to document something that I'm going to remove. This is
the first checking with all the defining words for the insns. I "cleverly"
tried to share code between registers and reg-pairs, for the inc/dec
(really inr/dcr/inx/dcx) insns, and for movi (mvi, lxi). Things as defined
will work fine for inc/dec, but I neglected to compile the 8- or 16-bit
immed value, and realized that it's too much trouble and complication.

So I'm retreating back to inc/dec for 8bits; incx/decx for 16 (pairs); and,
oddly, I think I'm going to go with li/lix for "load immediate/load imm
extended (or index, if you prefer). movi/movix, mvi/mvix are too clumsy.
And the current convention is that 16bit insns (excepting push and pop)
have an x extension: addx, incx/decx. Now lix. ;-)

If you want this code, it's in this checkin. After this it's going away.

I am happier about the neat way I define add/addi and all the other 2ops
all at once.


git-svn-id: 5ed59ae1b86916442d7930b9aaacd01318cc3510@664 f1bc7e2d-46f1-0310-96be-f91141564092

nickhen/muforth,nickhen/muforth