ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes

This SoC is integrated with 4 Cortex-A9 cores.  The GIC bindings
document says that the bits[15:8] of the 3rd cell of the interrupts
property represents PPI interrupt CPU mask.  Because the timer
interrupts are wired to all of the 4 cores, bits[15:8] should be set
to 0xf.

Signed-off-by: Masahiro Yamada <378b411a8a63ecc7605ec4272234862d7781c6ae@socionext.com>
Signed-off-by: Olof Johansson <8c69ee23f3f44f8162a64d579c1fa25c2f55298a@lixom.net>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs