mem: Fix MSHR assert triggering for invalidated prefetches
mem: Fix MSHR assert triggering for invalidated prefetches

This changeset updates an assert in src/mem/cache/mshr.cc which was
erroneously catching invalidated prefetch requests. These requests can
become invalidated if another component writes (an exclusive access)
to this location during the time that the read request is in
flight. The original assert made the assumption that these cases can
only occur for reads generated by the CPU, and hence
prefetcher-generated requests would sometimes trip the assert.

Change-Id: If4f043273a688c2bab8f7a641192a2b583e7b20e
Reviewed-by: Nikos Nikoleris <b6a1b3cd9d36c44e9eeb16bc870df3cb2a0cf469@arm.com>
Signed-off-by: Andreas Sandberg <c9f5686ee5bd561c93f9de79681eee75bfa7f36e@arm.com>

powerjg/gem5-ci-test,powerjg/gem5-ci-test,HwisooSo/gemV-update,gem5/gem5,TUD-OS/gem5-dtu,sobercoder/gem5,TUD-OS/gem5-dtu,rallylee/gem5,gedare/gem5,sobercoder/gem5,gem5/gem5,powerjg/gem5-ci-test,rallylee/gem5,sobercoder/gem5,gem5/gem5,Weil0ng/gem5,gedare/gem5,KuroeKurose/gem5,Weil0ng/gem5,KuroeKurose/gem5,HwisooSo/gemV-update,sobercoder/gem5,Weil0ng/gem5,Weil0ng/gem5,rallylee/gem5,HwisooSo/gemV-update,TUD-OS/gem5-dtu,HwisooSo/gemV-update,gedare/gem5,HwisooSo/gemV-update,gem5/gem5,Weil0ng/gem5,rallylee/gem5,gedare/gem5,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,gem5/gem5,powerjg/gem5-ci-test,rallylee/gem5,TUD-OS/gem5-dtu,gedare/gem5,HwisooSo/gemV-update,KuroeKurose/gem5,powerjg/gem5-ci-test,Weil0ng/gem5,gedare/gem5,Weil0ng/gem5,KuroeKurose/gem5,HwisooSo/gemV-update,powerjg/gem5-ci-test,rallylee/gem5,sobercoder/gem5,gedare/gem5,TUD-OS/gem5-dtu,rallylee/gem5,KuroeKurose/gem5,TUD-OS/gem5-dtu,gem5/gem5,KuroeKurose/gem5,KuroeKurose/gem5,sobercoder/gem5,sobercoder/gem5,gem5/gem5