drm/i915/skl: Program PLL for edp1.4 intermediate frequencies
drm/i915/skl: Program PLL for edp1.4 intermediate frequencies

v2: Making the link_clock half in switch inline with the DPLL_CTRL1_* macros
(Ville)

Signed-off-by: Sonika Jindal <cd61f9fbc6d7aeabe3269febf35c0efd90c23268@intel.com>
Reviewed-by: Ville Syrjälä <cd6e8d405ca90be3a03d5427c5b24fbd2d68dcc4@linux.intel.com>
Signed-off-by: Daniel Vetter <c1b6782c4af8f0673da8923a0702a1832e5940f4@ffwll.ch>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs