BaseTools/GenFw: ignore dynamic RELA sections
BaseTools/GenFw: ignore dynamic RELA sections

When building PIE (ET_DYN) executables, an additional RELA section is
emitted (in addition to the per-section .rela.text and .rela.data sections)
that is intended to be resolved at runtime by a ET_DYN compatible loader.

At the moment, due to the fact that we don't support GOT based relocations,
this dynamic RELA section only contains relocations that are redundant,
i.e., each R_xxx_RELATIVE relocation it contains duplicates a R_xxx_xx64
relocation appearing in .rela.text or .rela.data, and so we can simply
ignore this section (and we already ignore it in practice due to the fact
that it points to the NULL section, which has the SHF_ALLOC bit cleared).

For example,

  Section Headers:
    [Nr] Name              Type             Address           Offset
         Size              EntSize          Flags  Link  Info  Align
    [ 0]                   NULL             0000000000000000  00000000
         0000000000000000  0000000000000000           0     0     0
    [ 1] .text             PROGBITS         0000000000000240  000000c0
         000000000000427c  0000000000000008  AX       0     0     64
    [ 2] .rela.text        RELA             0000000000000000  00009310
         0000000000001bf0  0000000000000018   I       7     1     8
    [ 3] .data             PROGBITS         00000000000044c0  00004340
         00000000000046d0  0000000000000000  WA       0     0     64
    [ 4] .rela.data        RELA             0000000000000000  0000af00
         0000000000000600  0000000000000018   I       7     3     8
    [ 5] .rela             RELA             0000000000008bc0  00008a10
         0000000000000600  0000000000000018           0     0     8
    [ 6] .shstrtab         STRTAB           0000000000000000  0000b500
         0000000000000037  0000000000000000           0     0     1
    [ 7] .symtab           SYMTAB           0000000000000000  00009010
         0000000000000210  0000000000000018           8    17     8
    [ 8] .strtab           STRTAB           0000000000000000  00009220
         00000000000000eb  0000000000000000           0     0     1

  Relocation section '.rela.data' at offset 0xaf00 contains 64 entries:
    Offset          Info           Type           Sym. Value    Sym. Name + Addend
  000000004800  000100000001 R_X86_64_64       0000000000000240 .text + 3f5b
  000000004808  000100000001 R_X86_64_64       0000000000000240 .text + 3f63
  000000004810  000100000001 R_X86_64_64       0000000000000240 .text + 3f79
  000000004818  000100000001 R_X86_64_64       0000000000000240 .text + 3f90
  000000004820  000100000001 R_X86_64_64       0000000000000240 .text + 3fa6
  ...

  Relocation section '.rela' at offset 0x8a10 contains 64 entries:
    Offset          Info           Type           Sym. Value    Sym. Name + Addend
  000000004800  000000000008 R_X86_64_RELATIVE                    419b
  000000004808  000000000008 R_X86_64_RELATIVE                    41a3
  000000004810  000000000008 R_X86_64_RELATIVE                    41b9
  000000004818  000000000008 R_X86_64_RELATIVE                    41d0
  000000004820  000000000008 R_X86_64_RELATIVE                    41e6
  000000004828  000000000008 R_X86_64_RELATIVE                    41ff
  ...

Note that GOT based relocations result in entries that *only* appear in the
dynamic .rela section and not in .rela.text or .rela.data. This means two
things if we intend to add support for GOT based relocations:
- we must check that a dynamic RELA section exists;
- we must filter out duplicates between .rela and .rela.xxx, to prevent
  emitting duplicate fixups into the PE/COFF .reloc section.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org>
Reviewed-by: Liming Gao <6480311aeeb4b006862f6d13ebabddc03f51e507@intel.com>

MattDevo/edk2,MattDevo/edk2,MattDevo/edk2,MattDevo/edk2,MattDevo/edk2,MattDevo/edk2,MattDevo/edk2,MattDevo/edk2