Optimal memory layout found. By compiling with ptx code generation, we see the following:
Optimal memory layout found.
By compiling with ptx code generation, we see the following:

We first believed that interleaving would be useful, since the values of "a" and "b" would be on the same memory line, so a thread could read both from the same ld instruction, but this is not the case.
By checking the ptx, we see that there are several ld instructions, one for each operand, and so having "a" and "b" on the same line doesn't help, as there are still 2 ld operations done to fetch them.

A better technique is to use "normal" addition in a coalesced way. There are still 2 ld operations, but since the memory "line" is not as "wide" as for the interleaved method, less overall memory lines will have to be read.

Check with andrea for function calls, because right now, we cannot really call a function like "multiply these 2 numbers", because we are working in width instead of height

sahandKashani/CUDA-multiprecision-arithmetic-code-generator,sahandKashani/CUDA-multiprecision-arithmetic-code-generator