Sim: Fix Simulation.py to allow more than 1 core for standard switching.
Sim: Fix Simulation.py to allow more than 1 core for standard switching.

This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1,
switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are
assigned only once, after switch_cpus and switch_cpus_1 are constructed.

samueldotj/TeeRISC-Simulator,gem5/gem5,aclifton/cpeg853-gem5,markoshorro/gem5,sobercoder/gem5,briancoutinho0905/2dsampling,gem5/gem5,austinharris/gem5-riscv,austinharris/gem5-riscv,SanchayanMaity/gem5,aclifton/cpeg853-gem5,Weil0ng/gem5,zlfben/gem5,zlfben/gem5,rallylee/gem5,powerjg/gem5-ci-test,gedare/gem5,qizenguf/MLC-STT,rjschof/gem5,SanchayanMaity/gem5,HwisooSo/gemV-update,rallylee/gem5,gedare/gem5,joerocklin/gem5,powerjg/gem5-ci-test,TUD-OS/gem5-dtu,yb-kim/gemV,joerocklin/gem5,Weil0ng/gem5,qizenguf/MLC-STT,SanchayanMaity/gem5,aclifton/cpeg853-gem5,HwisooSo/gemV-update,kaiyuanl/gem5,aclifton/cpeg853-gem5,yb-kim/gemV,briancoutinho0905/2dsampling,Weil0ng/gem5,yb-kim/gemV,yb-kim/gemV,kaiyuanl/gem5,TUD-OS/gem5-dtu,TUD-OS/gem5-dtu,sobercoder/gem5,briancoutinho0905/2dsampling,qizenguf/MLC-STT,powerjg/gem5-ci-test,gedare/gem5,sobercoder/gem5,briancoutinho0905/2dsampling,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,aclifton/cpeg853-gem5,austinharris/gem5-riscv,joerocklin/gem5,samueldotj/TeeRISC-Simulator,aclifton/cpeg853-gem5,briancoutinho0905/2dsampling,HwisooSo/gemV-update,kaiyuanl/gem5,sobercoder/gem5,markoshorro/gem5,briancoutinho0905/2dsampling,zlfben/gem5,qizenguf/MLC-STT,sobercoder/gem5,powerjg/gem5-ci-test,gedare/gem5,KuroeKurose/gem5,rjschof/gem5,samueldotj/TeeRISC-Simulator,sobercoder/gem5,KuroeKurose/gem5,rallylee/gem5,HwisooSo/gemV-update,qizenguf/MLC-STT,briancoutinho0905/2dsampling,Weil0ng/gem5,KuroeKurose/gem5,austinharris/gem5-riscv,gedare/gem5,KuroeKurose/gem5,austinharris/gem5-riscv,rjschof/gem5,yb-kim/gemV,cancro7/gem5,rallylee/gem5,joerocklin/gem5,KuroeKurose/gem5,markoshorro/gem5,markoshorro/gem5,TUD-OS/gem5-dtu,zlfben/gem5,gem5/gem5,SanchayanMaity/gem5,cancro7/gem5,cancro7/gem5,rjschof/gem5,yb-kim/gemV,yb-kim/gemV,joerocklin/gem5,gem5/gem5,gedare/gem5,kaiyuanl/gem5,rallylee/gem5,gem5/gem5,gem5/gem5,markoshorro/gem5,rjschof/gem5,HwisooSo/gemV-update,SanchayanMaity/gem5,qizenguf/MLC-STT,rjschof/gem5,zlfben/gem5,cancro7/gem5,rallylee/gem5,kaiyuanl/gem5,austinharris/gem5-riscv,HwisooSo/gemV-update,TUD-OS/gem5-dtu,cancro7/gem5,HwisooSo/gemV-update,rjschof/gem5,samueldotj/TeeRISC-Simulator,joerocklin/gem5,SanchayanMaity/gem5,kaiyuanl/gem5,cancro7/gem5,gedare/gem5,samueldotj/TeeRISC-Simulator,joerocklin/gem5,markoshorro/gem5,aclifton/cpeg853-gem5,austinharris/gem5-riscv,qizenguf/MLC-STT,Weil0ng/gem5,Weil0ng/gem5,joerocklin/gem5,TUD-OS/gem5-dtu,samueldotj/TeeRISC-Simulator,zlfben/gem5,Weil0ng/gem5,samueldotj/TeeRISC-Simulator,sobercoder/gem5,powerjg/gem5-ci-test,powerjg/gem5-ci-test,KuroeKurose/gem5,yb-kim/gemV,rallylee/gem5,kaiyuanl/gem5,SanchayanMaity/gem5,gem5/gem5,cancro7/gem5,KuroeKurose/gem5,markoshorro/gem5,zlfben/gem5