GPIO: Fix access/wait/packet signals in AXI module
GPIO: Fix access/wait/packet signals in AXI module

Need mux for rd_access and wr_access.

Signed-off-by: Ola Jeppsson <793f970c52ded1276b9264c742f19d1888cbaf73@adapteva.com>

olajep/oh,peteasa/oh,parallella/oh,parallella/oh,parallella/oh,olajep/oh,peteasa/oh,parallella/oh,peteasa/oh,olajep/oh,peteasa/oh,olajep/oh