drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv

For disabling L3 clock gating we need to set bit 25 of MMIO
register 940c. Earlier this was being done by just writing 1
into bit 25 and resetting all other bits.
This patch modifies the routine to read-modify-write of the
register, so that the values of other bits are not destroyed.

v2: Modifying the comments and the patch commit message (Chris)

Signed-off-by: Akash Goel <43c08a34c75a22c720e674b49d601292087a879d@intel.com>
Signed-off-by: Sourab Gupta <f8c1e02e2aced2a829e1c894f7418daa2b0d2f0e@intel.com>
Reviewed-by: Damien Lespiau <64bd3cb94f359c1a3ce68dae5e26b40578526277@intel.com>
[danvet: Apply checkpatch fixup.]
Signed-off-by: Daniel Vetter <c1b6782c4af8f0673da8923a0702a1832e5940f4@ffwll.ch>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs