clk: tegra124: Add init data for dsi lp clocks
clk: tegra124: Add init data for dsi lp clocks

Set the parent of the dsi lp clocks to pll_p and the rate
to 68MHz. The default parent is clk_m and rate is 12MHz, this
is too slow to receive data from the peripheral.

Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz
will suffice.

Signed-off-by: Sean Paul <f9352ecf3e2294bdb914c99cca8d12601acec118@chromium.org>
Signed-off-by: Peter De Schrijver <651dda1e35c6fe8f72c3112540c405a2364bcd71@nvidia.com>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs