gpu: ipu-v3: limit pixel clock divider to 8-bits
gpu: ipu-v3: limit pixel clock divider to 8-bits

The DI pixel clock divider bit field is only 8 bits wide for the
integer part, so limit the divider to the 1...255 interval before
deciding whether the internal clock can be used and before writing
to the register.

Reported-by: Felix Mellmann <8256ca82fdba5f93c1c9cd77341dc74a55f4837c@gmail.com>
Signed-off-by: Philipp Zabel <db7328bbf81a38b011e8d0f5302fd54c788d0608@pengutronix.de>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs