Cr50: I2CS: Clear IRQ at beginning of ISR
Cr50: I2CS: Clear IRQ at beginning of ISR

If the host sends a back to back I2CS write followed by a read of the
access register, then the read IRQ can be missed by FW because it was
clearing this bit at the end of the ISR. This would result in a
following write to have the incorrect number of bytes since the
address register byte from the read that wasn't processed gets left in
the HW write fifo.

BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
The issue was happening at the beginning of depthcharge. Without this
fix, I would see the Cr50 console message:
'data size mismatch for reg 0x0 rx 2, need 1'
After moving the IRQ clear could not reproduce this message. In
addition, the debug I2CS log showed that there was a read transaction
immediately following the write.

Change-Id: I9854dde6880a789e0acb2b1f6a06b43c73a5a2df
Signed-off-by: Scott <7d40b3eb9e17bf55d972074a5e77a7ea4159f9dd@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382687
Commit-Ready: Scott Collyer <7d40b3eb9e17bf55d972074a5e77a7ea4159f9dd@chromium.org>
Tested-by: Scott Collyer <7d40b3eb9e17bf55d972074a5e77a7ea4159f9dd@chromium.org>
Reviewed-by: Randall Spangler <62698fdbb84d1779579ee80c3f39fac22017e5bc@chromium.org>
Reviewed-by: Vadim Bendebury <5515d6d2d0829cbe0dd0dcf2094aaded06d58514@chromium.org>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec