[mgsim] fixed allocate/create/sync register writeback race condition
[mgsim] fixed allocate/create/sync register writeback race condition

The register writeback on allocate, create and sync happens via a seperate queue and process from the pipeline. It was possible that the instruction that scheduled the event that causes the writeback does not write back Pending to the register file before the completion writeback is written back. Then, the Pending write back would overwrite the result and the system would eventually deadlock.

To fix this, the separate writeback process must wait with writing back until the target register is Pending or Waiting, which means that the issuing instruction has run through the pipeline.


git-svn-id: 5df9d7b5f7c0affc7b6f3523bb99fcf0586782cc@3916 e97e5017-a994-416e-809d-76780e9f78db

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