risugen: allow shift by 4 in reg_plus_reg_shifted
risugen: allow shift by 4 in reg_plus_reg_shifted

aarch64 SIMD/fp instruction variants require addressing
in the form register plus register shifted by 4, to align
128bit data.

Signed-off-by: Claudio Fontana <5fe97b97070bc75ff3c7a6b130e2dcc62cbb9b58@linaro.org>

vivier/risu,stsquad/risu,vivier/risu,stsquad/risu,stsquad/risu