i965/gen4-5: Set ENDIF dst and src0 fields to the null register.
i965/gen4-5: Set ENDIF dst and src0 fields to the null register.

The hardware docs don't mention explicitly what these fields should
be, but I've verified experimentally on ILK that using a GRF as
destination causes the register to be corrupted when the execution
size of an ENDIF instruction is higher than 8 -- and because the
destination we were using was g0, eventually a hang.

Fixes some 150 piglit tests on Gen4-5 when forced to run shaders with
if conditionals 16-wide, e.g. shaders/glsl-fs-sampler-numbering-3.

Reviewed-by: Matt Turner <789b315743a28dd066a4ba1459c35951c291d8a6@gmail.com>
Reviewed-by: Kenneth Graunke <bd2562f754ec92342f93f61c25d731e290a2ffa8@whitecape.org>

metora/MesaGLSLCompiler,metora/MesaGLSLCompiler,metora/MesaGLSLCompiler