cortex-m0: add more constraints on atomic implementation
cortex-m0: add more constraints on atomic implementation

In ARMv6-m instruction set, the load/store address register can only be
a "low" register : r0..r7.
Update the inline assembly constraints to match the hardware.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=make buildall

Reviewed-on: https://chromium-review.googlesource.com/224582
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit ba98b92bbb03a62a466a36fbb50843a37602d98d)
Signed-off-by: Duncan Laurie <70662b43bc1a20b57ded72a2b08be88dd0da4841@chromium.org>

Change-Id: I9872aeb437b2bb6401bed8076348e26d434320dd
Reviewed-on: https://chromium-review.googlesource.com/225728
Tested-by: Duncan Laurie <70662b43bc1a20b57ded72a2b08be88dd0da4841@chromium.org>
Reviewed-by: Duncan Laurie <70662b43bc1a20b57ded72a2b08be88dd0da4841@chromium.org>
Commit-Queue: Duncan Laurie <70662b43bc1a20b57ded72a2b08be88dd0da4841@chromium.org>

thehobn/ec,thehobn/ec,thehobn/ec,thehobn/ec