Bug fix: erx pipeline misalignment -access signal happens one signal after empty goes low to compensate for fifo data latency -verify that this is how the Xilinx FIFO works as well.
Bug fix: erx pipeline misalignment
-access signal happens one signal after empty goes low to compensate for fifo data latency
-verify that this is how the Xilinx FIFO works as well.

peteasa/oh,olajep/oh,peteasa/oh,peteasa/oh,parallella/oh,peteasa/oh,olajep/oh,parallella/oh,parallella/oh,olajep/oh,olajep/oh,parallella/oh