recover_adder: Replace XOR3 and MAJ gates with structural Verilog
recover_adder: Replace XOR3 and MAJ gates with structural Verilog

This way, they generate the uppercase cells rather than the lowercase
cells, and it is possible to directly run abc afterwards. Before this
change, it would be necessary to run simplemap first, which might
destroy some other cells that have been recovered.

azonenberg/yosys,azonenberg/yosys,azonenberg/yosys,azonenberg/yosys,azonenberg/yosys,azonenberg/yosys,azonenberg/yosys,azonenberg/yosys,azonenberg/yosys