[ci] Print FPGA synth and impl logs to stdout while running
[ci] Print FPGA synth and impl logs to stdout while running

Due to a FuseSoC change sometime last year, Edalize no longer outputs
the backends log to stdout by default.

However, getting these logs is very useful when debugging CI/FPGA issues
(as the FPGA runs may take so long). For this reason, this commit
changes CI to call fusesoc with the `--verbose` flag for the FPGA runs.

Signed-off-by: Pirmin Vogel <386a7fc8e7338ed7899b4d9883c0ebec5de81366@lowrisc.org>

lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan