/* Copyright (c) 2013, Linaro Limited
 * All rights reserved.
 *
 * SPDX-License-Identifier:     BSD-3-Clause
 */


/**
 * @file
 *
 * ODP synchronisation
 */

#ifndef ODP_SYNC_H_
#define ODP_SYNC_H_

#ifdef __cplusplus
extern "C" {
#endif


/**
 * Synchronise stores
 *
 * Ensures that all CPU store operations that precede the odp_sync_stores()
 * call are globally visible before any store operation that follows it.
 */
static inline void odp_sync_stores(void)
{
#if defined __x86_64__ || defined __i386__

	__asm__  __volatile__ ("sfence\n" : : : "memory");

#elif defined __arm__

	__asm__ __volatile__ ("dmb st" : : : "memory");

#elif defined __OCTEON__

	__asm__  __volatile__ ("syncws\n" : : : "memory");

#else
	__sync_synchronize();
#endif
}


#ifdef __cplusplus
}
#endif

#endif

/* Copyright (c) 2013, Linaro Limited
 * All rights reserved.
 *
 * SPDX-License-Identifier:     BSD-3-Clause
 */


/**
 * @file
 *
 * ODP synchronisation
 */

#ifndef ODP_SYNC_H_
#define ODP_SYNC_H_

#ifdef __cplusplus
extern "C" {
#endif


/**
 * Synchronise stores
 *
 * Ensures that all CPU store operations that precede the odp_sync_stores()
 * call are globally visible before any store operation that follows it.
 */
static inline void odp_sync_stores(void)
{
#if defined __x86_64__ || defined __i386__

	__asm__  __volatile__ ("sfence\n" : : : "memory");

#elif defined __arm__ || defined __aarch64__

	__asm__ __volatile__ ("dmb st" : : : "memory");

#elif defined __OCTEON__

	__asm__  __volatile__ ("syncws\n" : : : "memory");

#else
	__sync_synchronize();
#endif
}


#ifdef __cplusplus
}
#endif

#endif

Add write memory barrier for aarch64
Add write memory barrier for aarch64

This patch updates odp_sync_stores routine to add write memory barrier for
aarch64.

Signed-off-by: Ankit Jindal <0920ec6e02c95b572519373847b995b0763a0743@linaro.org>
Signed-off-by: Tushar Jagad <3604ae1aed16529df1f2280ecebda0599cb1687d@linaro.org>
Reviewed-by: Anders Roxell <b4e8e89057bc64bc4f9625a4a821c9ac177a7ed2@linaro.org>
