/* Copyright 2021 The Chromium OS Authors. All rights reserved.
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */

#ifndef ZEPHYR_SHIM_INCLUDE_BBRAM_H_
#define ZEPHYR_SHIM_INCLUDE_BBRAM_H_

/**
 * Layout of the battery-backed RAM region.
 * TODO (b:178807203) Migrate these values to devicetree registers.
 */
enum bbram_data_index {
	/** General-purpose scratchpad */
	BBRM_DATA_INDEX_SCRATCHPAD = 0,
	/** Saved reset flags */
	BBRM_DATA_INDEX_SAVED_RESET_FLAGS = 4,
	/** Wake reasons for hibernate */
	BBRM_DATA_INDEX_WAKE = 8,
	/** USB-PD saved port0 state */
	BBRM_DATA_INDEX_PD0 = 12,
	/** USB-PD saved port1 state */
	BBRM_DATA_INDEX_PD1 = 13,
	/** Vboot EC try slot */
	BBRM_DATA_INDEX_TRY_SLOT = 14,
	/** USB-PD saved port2 state */
	BBRM_DATA_INDEX_PD2 = 15,
	/** VbNvContext for ARM arch */
	BBRM_DATA_INDEX_VBNVCNTXT = 16,
	/** RAM log for Booter */
	BBRM_DATA_INDEX_RAMLOG = 32,
	/** Flag to indicate validity of panic data starting at index 36. */
	BBRM_DATA_INDEX_PANIC_FLAGS = 35,
	/** Panic data (index 35-63)*/
	BBRM_DATA_INDEX_PANIC_BKUP = 36,
	/** The start time of LCT(4 bytes) */
	BBRM_DATA_INDEX_LCT_TIME = 64,
};

#endif /* ZEPHYR_SHIM_INCLUDE_BBRAM_H_ */

Add battery-backed RAM constants for npcx
zephyr: Add battery-backed RAM constants for npcx

Bring in the battery-backed RAM layout for npcx. This change
includes a TODO to migrate these values to devicetree registers
but since system.c is on the critical path, this will be a good
step in the right direction.

BRANCH=none
BUG=b:176828988, b:174481378
TEST=zmake testall

Signed-off-by: Yuval Peress <50dc11c009bd4d7e9d9d15a383c1743ce5ee82ef@chromium.org>
Change-Id: Ib84bf4f680c74a95a8549f57c30dab7fca3db42c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2659681
Commit-Queue: Simon Glass <c00b0378376498bd9cd974c388df8854c0131d27@chromium.org>
Reviewed-by: Simon Glass <c00b0378376498bd9cd974c388df8854c0131d27@chromium.org>
