Nellyw888
/

VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb

Reinforcement Learning

text-generation

text-generation-inference

Model card Files Files and versions Community

Nellyw888 commited on May 31

Commit

3b93ce1

·

verified ·

1 Parent(s): 4d284a3

Update README.md

Files changed (1) hide show

README.md +1 -1

README.md CHANGED Viewed

@@ -14,7 +14,7 @@ base_model:
 # VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb
-For implementation details, visit our GitHub repository: [VeriReason](https://github.com/NellyW8/VeriReason)
 Check out our paper: [VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation](https://arxiv.org/abs/2505.11849)

 # VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb
+For implementation details, visit our GitHub repository: [VeriReason](https://github.com/NellyW8/VeriReason) and our [page](https://nellyw8.github.io/VeriReason/)
 Check out our paper: [VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation](https://arxiv.org/abs/2505.11849)